Series of Intellectual Property Blocks for Altera FPGA
The IP solutions from Mpression offer IP blocks targeted at Altera FPGA devices to reduce development time and resources at customer FPGA projects. Each solution consists of not only a hardware IP core but also its peripheral technologies and software technologies such as drivers for the IP.
The V-by-One®HS is a leading-edge high speed interface technology which THine Electronics, Inc. developed and specified for Flat Panel Display markets.Implementing the V-by-One®HS Functional IP on to ALTERA FPGAs that Macnica team offers enables the FPGA based V-by-One® HS technology to offer higher frame rates and higher resolutions for FPDs. The IP has 2 kinds, the transmitter IP and the receiver IP. This makes it possible to reduce the cost considerably comparing with the conventional technology like LVDS.
By using our GigE Vision IP, you can transfer input image data, which is read from image sensor etc., to Gigabit Ethernet network easily and timely in accordance with GigE Vision protocol. As effective transfer rate, 995Mbps can be accomplished, it is almost equal to Gigabit Ethernet's maximum bandwidth 1Gbps. In addition, you can build highly reliable system because image gap areas arisen from defect packets and packet losses are repairable by using packet resend function. The GigE Vision IP is suitable for various image transfer related applications which make the fullest possible use of Gigabit Ethernet like high resolution machine vision camera, high frame rate security camera, medical imaging system required high reliability, and so on.
Graphic Controller IP can draw multiple graphic images on top of input image in real time. As a graphic image, both existing bitmap images and drawn images by itself can be used. You can overlay such graphic images up to 4 layers with alpha blending functionality at any transparency. By using this IP, you can easily achieve various On-Screen-Display solutions like start-up logo, menu, icon, character, and so on.